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8725ayi-01 www.idt.com rev. a august 9, 2010 1 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator g eneral d escription the ics8725i-01 is a highly versatile 1:5 differential-to- hstl clock generator. the ics8725i-01 has a fully integrated pll and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 31.25mhz to 630mhz. the reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. the external feedback allows the device to achieve ?zero delay? between the input clock and the output clocks. the pll_sel pin can be used to bypass the pll for system test and debug purposes. in bypass mode, the reference clock is routed around the pll and into the internal output dividers. b lock d iagram p in a ssignment f eatures ? 5 differential hstl outputs ? selectable differential clkx, nclkx input pairs ? clkx, nclkx pairs can accept the following differential input levels: lvds, lvpecl, hstl, sstl, hcsl ? output frequency range: 31.25mhz to 630mhz ? input frequency range: 31.25mhz to 630mhz ? vco range: 250mhz to 630mhz ? external feedback for ?zero delay? clock regeneration with configurable frequencies ? programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 ? static phase offset: 30ps 125ps ? cycle-to-cycle jitter: 35ps (maximum) ? output skew: 50ps (maximum) ? 3.3v core, 1.8v output operating supply ? -40c to 85c ambient operating temperature 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 v ddo q3 nq3 q2 nq2 q1 nq1 v ddo sel0 sel1 clk0 nclk0 clk1 nclk1 clk_sel mr v ddo q0 nq0 gnd sel2 fb_in nfb_in v dd v ddo nq4 q4 gnd sel3 v dda pll_sel v dd ics8725i-01 pll_sel clk0 nclk0 clk1 nclk1 clk_sel fb_in nfb_in sel0 sel1 sel2 sel3 mr q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 0 1 pll 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 0 1 1, 2, 4, 8, 16, 32 , 64 ? available in both standard (rohs5) and lead-free (rohs 6) packages
8725ayi-01 www.idt.com rev. a august9, 2010 2 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator t able 1. p in d escriptions r e b m u ne m a ne p y tn o i t p i r c s e d , 2 , 1 9 2 , 2 1 , 1 l e s , 0 l e s 3 l e s , 2 l e s t u p n in w o d l l u p . 3 e l b a t n i s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 30 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 40 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 51 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 61 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 7l e s _ k l ct u p n in w o d l l u p . 1 k l c n , 1 k l c s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l . 0 k l c n , 0 k l c s t c e l e s , w o l n e h w 8r mt u p n in w o d l l u p t e s e r e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a o g o t x q n s t u p t u o d e t r e v n i e h t d n a w o l o g o t x q s t u p t u o e u r t e h t g n i s u a c . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h . s l e v e l e c a f r e t n i l t t v l / s o m c v l 2 3 , 9v d d r e w o p. s n i p y l p p u s e r o c 0 1n i _ b f nt u p n ip u l l u p . " y a l e d o r e z " h t i w s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f 1 1n i _ b ft u p n in w o d l l u p . " y a l e d o r e z " h t i w s k c o l c g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f 8 2 , 3 1d n gr e w o p. d n u o r g y l p p u s r e w o p 5 1 , 4 10 q , 0 q nt u p t u o. s l e v e l e c a f r e t n i l t s h . r i a p t u p t u o l a i t n e r e f f i d , 7 1 , 6 1 5 2 , 4 2 v o d d r e w o p. s n i p y l p p u s t u p t u o 9 1 , 8 11 q , 1 q nt u p t u o. s l e v e l e c a f r e t n i l t s h . r i a p t u p t u o l a i t n e r e f f i d 1 2 , 0 22 q , 2 q nt u p t u o. s l e v e l e c a f r e t n i l t s h . r i a p t u p t u o l a i t n e r e f f i d 3 2 , 2 23 q , 3 q nt u p t u o. s l e v e l e c a f r e t n i l t s h . r i a p t u p t u o l a i t n e r e f f i d 7 2 , 6 24 q , 4 q nt u p t u o. s l e v e l e c a f r e t n i l t s h . r i a p t u p t u o l a i t n e r e f f i d 0 3v a d d r e w o p. n i p y l p p u s g o l a n a 1 3l e s _ l l pt u p n ip u l l u p . s r e d i v i d e h t o t t u p n i e h t s a k c o l c e c n e r e f e r d n a l l p e h t n e e w t e b s t c e l e s . l l p s t c e l e s , h g i h n e h w . k c o l c e c n e r e f e r s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l : e t o n p u l l u p d n a w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r n t able 2. p in c haracteristics l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k
8725ayi-01 www.idt.com rev. a august 9, 2010 3 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator t able 3a. c ontrol i nput f unction t able s t u p n i s t u p t u o 1 = l e s _ l l p e d o m e l b a n e l l p 3 l e s2 l e s1 l e s0 l e s* ) z h m ( e g n a r y c n e u q e r f e c n e r e f e r4 q n : 0 q n , 4 q : 0 q 0000 0 3 6 - 0 5 21 000 1 5 1 3 - 5 2 11 00 10 5 . 7 5 1 - 5 . 2 61 00 11 5 7 . 8 7 - 5 2 . 1 31 0100 0 3 6 - 0 5 22 0101 5 1 3 - 5 2 12 0110 5 . 7 5 1 - 5 . 2 62 0111 0 3 6 - 0 5 24 10 0 0 5 1 3 - 5 2 14 10 0 1 0 3 6 - 0 5 28 10 10 5 1 3 - 5 2 12 x 10 1 1 5 . 7 5 1 - 5 . 2 62 x 1100 5 7 . 8 7 - 5 2 . 1 32 x 110 1 5 . 7 5 1 - 5 . 2 64 x 1110 5 7 . 8 7 - 5 2 . 1 34 x 1111 5 7 . 8 7 - 5 2 . 1 38 x . z h m 0 3 6 o t z h m 0 5 2 s i e v o b a s n o i t a r u g i f n o c l l a r o f e g n a r y c n e u q e r f o c v : e t o n * t able 3b. pll b ypass f unction t able s t u p n i s t u p t u o 0 = l e s _ l l p e d o m s s a p y b l l p 3 l e s2 l e s1 l e s0 l e s4 q n : 0 q n , 4 q : 0 q 00 0 0 4 00 0 1 4 00 10 4 00 1 1 8 0100 8 010 1 8 0110 6 1 0111 6 1 10 0 0 2 3 10 0 1 4 6 10 1 0 2 10 1 1 2 110 0 4 110 1 1 11 10 2 11 1 1 1
8725ayi-01 www.idt.com rev. a august9, 2010 4 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator t able 4c. d ifferential dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c t able 4a. p ower s upply dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o6 . 18 . 10 . 2v i d d t n e r r u c y l p p u s r e w o p 7 3 1a m i a d d t n e r r u c y l p p u s g o l a n a 7 1a m i o d d t n e r r u c y l p p u s t u p t u od a o l o n0a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t u p n i t n e r r u c h g i h n i _ b f , 1 k l c , 0 k l cv d d v = n i v 5 6 4 . 3 =0 5 1a n i _ b f n , 1 k l c n , 0 k l c nv d d v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l n i _ b f , 1 k l c , 0 k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a n i _ b f n , 1 k l c n , 0 k l c nv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0v d d 5 8 . 0 -v v s i x k l c n , x k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 1 e t o n d d . v 3 . 0 + v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 2 e t o n h i . t able 4b. lvcmos/lvttl dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 2v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 3 . 0 -8 . 0v i h i t n e r r u c h g i h t u p n i , 0 l e s , r m , l e s _ k l c 3 l e s , 2 l e s , 1 l e s v d d v = n i v 5 6 4 . 3 = v o d d v 2 = 0 5 1a l e s _ l l p v d d v = n i v 5 6 4 . 3 = v o d d v 2 = 5a i l i t n e r r u c w o l t u p n i , 0 l e s , r m , l e s _ k l c 3 l e s , 2 l e s , 1 l e s v d d , v 5 6 4 . 3 = v o d d v , v 2 = n i v 0 = 5 -a l e s _ l l p v d d , v 5 6 4 . 3 = v o d d v , v 2 = n i v 0 = 0 5 1 -a a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8725ayi-01 www.idt.com rev. a august 9, 2010 5 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator t able 4d. hstl dc c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h o ; e g a t l o v h g i h t u p t u o 1 e t o n 14 . 1v v l o ; e g a t l o v w o l t u p t u o 1 e t o n 04 . 0v v x o e g a t l o v r e v o s s o r c t u p t u o( x % 0 4v h o -v l o + )v l o v ( x % 0 6 h o v - l o v + ) l o v v g n i w s k a e p - o t - k a e p g n i w s e g a t l o v t u p t u o 6 . 01 . 1v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n . d n u o r g o t t able 5. i nput f requency c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f n i y c n e u q e r f t u p n i , 0 k l c n , 0 k l c 1 k l c n , 1 k l c 1 = l e s _ l l p5 2 . 1 30 3 6z h m 0 = l e s _ l l p0 3 6z h m t able 6. ac c haracteristics , v dd = v dda = 3.3v5%, v ddo = 1.8v0.2v, t a = -40c to 85c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 0 3 6z h m t d p 1 e t o n ; y a l e d n o i t a g a p o r p v 0 = l e s _ l l p ? z h m 0 3 6 4 . 39 . 35 . 4s n ) ? ( t5 , 2 e t o n ; t e s f f o e s a h p c i t a t sv 3 . 3 = l e s _ l l p5 9 -0 35 5 1s p t ) o ( k s5 , 3 e t o n ; w e k s t u p t u o 0 5s p t ) c c ( t i j6 , 5 e t o n ; r e t t i j e l c y c - o t - e l c y c 5 3s p t ) ? ( t i j6 , 5 , 4 e t o n ; r e t t i j e s a h p 0 5 s p t l e m i t k c o l l l p 1s m t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 0 7s p t w p h t d i w e s l u p t u p t u ot d o i r e p 5 8 - 2 /t d o i r e p 2 /t d o i r e p 5 8 + 2 /s p t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n l a n g i s t u p n i k c a b d e e f d e g a r e v a e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w , s n o i t i d n o c l l l a s s o r c a : 3 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d . s t n i o p s s o r c l a i t n e r e f f i d t u p t u o t a d e r u s a e m . d e s u e c r u o s t u p n i e h t n o t n e d n e p e d s i r e t t i j e s a h p : 4 e t o n . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 5 e t o n . z h m 2 2 6 f o y c n e u q e r f o c v t a d e z i r e t c a r a h c : 6 e t o n
8725ayi-01 www.idt.com rev. a august9, 2010 6 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator p arameter m easurement i nformation c ycle - to -c ycle j itter p hase j itter and s tatic p hase o ffset o utput r ise /f all t ime clock outputs 20% 80% 80% 20% t r t f v od t sk(o) nqx nq nqy qy d ifferential i nput l evel o utput s kew 3.3v c ore /1.8v o utput l oad ac t est c ircuit scope hstl qx nqx v cmr cross points v pp gnd clk0, clk1 nclk0, nclk1 v dd nq0:nq4 q0:q4 nclk0, nclk1 clk0, clk1 nq0:nq4 q0:q4 t pd v dd , v dda 0v 3.3v 5% v ddo 1.8v 0.2v o utput d uty c ycle /p ulse w idth /p eriod pulse width t period t pw t period odc = nq0:nq4 q0:q4 p ropagation d elay ? ? ? ? t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) t (?) mean = static phase offset ? ? t (?) v oh v ol v oh v ol nclk0, nclk1 nfb_in fb_in t jit(?) = t (?) ? t (?) mean = phase jitter clk0, clk1 gnd
8725ayi-01 www.idt.com rev. a august9, 2010 8 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator f igure 3c. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, hstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 3a. clk/ n clk i nput d riven by hstl d river examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for hstl drivers. if you are using an hstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
8725ayi-01 www.idt.com rev. a august 9, 2010 9 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator f igure 4a. ics8725i-01 hstl z ero d elay b uffer s chematic e xample l ayout g uideline the schematic of the ics8725i-01 layout example is shown in figure 4a. the ics8725i-01 recommended pcb board layout for this example is shown in figure 4b. this layout example is used as a general guideline. the layout in the actual system will c6 0.1uf vdda sel0 sel[3:0] = 0101, divide by 2 sel1 (u1-32) (u1-25) vddo vddo 3.3v 3.3v pecl driver rd4 sp ru3 1k c11 0.01u c4 0.1uf vdd ru7 sp c2 0.1uf c7 0.1uf sp = space (i.e. not intstalled) r2a 50 c1 0.1uf rd5 1k pll_sel clk_sel c16 10u r2b 50 vdd=3.3v vdd r7 10 pll_sel sel1 u1 8725_01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 sel0 sel1 clk0 nclk0 clk1 nclk1 clk_sel mr vdd nfb_in fb_in sel2 gnd nq0 q0 vddo vddo nq1 q1 nq2 q2 nq3 q3 vddo vdd pll_sel vdda sel3 gnd q4 nq4 vddo rd7 1k r4b 50 c5 0.1uf (u1-17) r8 50 zo = 50 ohm zo = 50 ohm ru6 1k (155.5 mhz) sel3 ru5 sp rd2 1k sel2 rd6 sp zo = 50 ohm r4a 50 ru2 sp sel3 vdd sel2 sel0 vdd zo = 50 ohm (155.5 mhz) (u1-16) ru4 1k vddo=1.8v (u1-9) lvhstl_input + - r9 50 rd3 sp bypass capacitors located near the power pins r10 50 clk_sel (u1-24) depend on the selected component types, the density of the components, the density of the traces, and the stacking of the p.c. board.
8725ayi-01 www.idt.com rev. a august9, 2010 10 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator f igure 4b. pcb b oard l ayout f or ics8725i-01 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors c1, c6, c2, c4, and c5, as close as possible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v dda pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the differential 50 output traces should have same length. ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock traces on the same layer. whenever pos- sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. ? make sure no other signal traces are routed between the clock trace pair. ? the matching termination resistors should be located as close to the receiver input pins as possible. c1 c2 c16 r7 gnd c5 vdd u1 vdda c4 50 ohm traces c11 via vddo pin 1 c7 c6
8725ayi-01 www.idt.com rev. a august 9, 2010 11 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ics8725i-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics8725i-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (137ma + 17ma) = 499mw ? power (outputs) max = 32.8mw/loaded output pair if all outputs are loaded, the total power is 5 * 32.8mw = 164mw total power _max (3.465v, with all outputs switching) = 499mw + 164mw = 663mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for the devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1c/w per table 7 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.663w * 42.1c/w = 113c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs. table 7. thermal resistance ja for 32-pin lqfp, forced convection
8725ayi-01 www.idt.com rev. a august9, 2010 12 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. hstl output driver circuit and termination are shown in figure 5. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load. pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = (v oh_min /r l ) * (v dd_max - v oh_min ) pd_l = (v ol_max /r l ) * (v dd_max - v ol_max ) pd_h = (1v/50 ) * (2v - 1v) = 20mw pd_l = (0.4v/50 ) * (2v - 0.4v) = 12.8mw total power dissipation per output pair = pd_h + pd_l = 32.8mw f igure 5. hstl d river c ircuit and t ermination v dd v out rl 50 q1
8725ayi-01 www.idt.com rev. a august 9, 2010 13 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator r eliability i nformation t ransistor c ount the transistor count for ics8725i-01 is: 2969 t able 8. ja vs . a ir f low t able ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8725ayi-01 www.idt.com rev. a august9, 2010 14 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator p ackage o utline - y s uffix t able 9. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
8725ayi-01 www.idt.com rev. a august 9, 2010 15 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator t able 10. o rdering i nformation r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - i y a 5 2 7 81 0 - i y a 5 2 7 8 s c ip f q l d a e l 2 3y a r tc 5 8 o t c 0 4 - t 1 0 - i y a 5 2 7 81 0 - i y a 5 2 7 8 s c ip f q l d a e l 2 3l e e r d n a e p a t 0 0 0 1c 5 8 o t c 0 4 - 1 0 - i y a 5 2 7 8l 1 0 i a 5 2 7 8 s c ip f q l e e r f - d a e l 2 3y a r tc 5 8 o t c 0 4 - t 1 0 - i y a 5 2 7 8l 1 0 i a 5 2 7 8 s c ip f q l e e r f - d a e l 2 3l e e r d n a e p a t 0 0 0 1c 5 8 o t c 0 4 - while the information presented herein has been checked for both accuracy and reliability, integrated device technology, inc. ( idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are impl ied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other extraordinary environmental requirement s are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use i n life support devices or critical medical instruments. note: parts that are ordered with an ""lf"" suffix to the part number are the pb-free configuration and are rohs compliant.
8725ayi-01 www.idt.com rev. a august9, 2010 16 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a0 1 t5 1g n i k r a m e e r f - d a e l d e d d a - n o i t a m r o f n i g n i r e d r o 7 0 / 9 1 / 2 1 a0 1 t5 1 7 1 . s c i m o r f t d i h t i w r e t o o f / r e d a e h s ' t e e h s a t a d d e t a d p u . n m u l o c r e b m u n r e d r o / t r a p m o r f x i f e r p s c i d e v o m e r . e g a p t c a t n o c d e d d a 0 1 / 9 / 8
8725ayi-01 www.idt.com rev. a august 9, 2010 17 ics8725i-01 1:5 d ifferential - to -hstl z ero d elay c lock g enerator we?ve got your timing solution. sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 tech support netcom@idt.com 6024 silver creek valley road san jose, ca 95138 ? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or m ay be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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